--------------------------------------------------------------------------------
-- Company: Synapse
-- Module Name:    memory - Behavioral
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity memory_sdram is
	Port (   	 address	: in	std_logic_vector (17 downto 0); 
                         dataOut		: out	std_logic_vector (15 downto 0); 
                         read			: in	std_logic;
			 vsync_n	: in	std_logic;
			 keyboard	: in	std_logic_vector(9 downto 0);
			 

		    -- SDRAM Interface Stuff
			
		    rd         : out std_logic; -- memory read control signal
		    dIn        : in  std_logic_vector(15 downto 0)                     -- data from memory
		     );

end memory_sdram;

architecture Behavioral of memory_sdram is


begin
       

process(read)

	
	begin

	          if (read = '0') then
                               if (address(17 downto 6) = "000011110001") then
					case address(5 downto 2) is
						-- W, S, A, D, UP, DOWN, LEFT, RIGHT, SPACE, ALT
						-- UP1, DOWN1, LEFT1, RIGHT1, UP2, DOWN2, LEFT2, RIGHT2, START, DEBUG
						when "0000" =>
							dataOut <= "000000000000000" & vsync_n;
						when "0001" =>
							dataOut <= "000000000000000" & keyboard(9);
						when "0010" =>
							dataOut <= "000000000000000" & keyboard(8);
						when "0011" =>
							dataOut <= "000000000000000" & keyboard(7);
						when "0100" =>
							dataOut <= "000000000000000" & keyboard(6);
						when "0101" =>
							dataOut <= "000000000000000" & keyboard(5);
						when "0110" =>
							dataOut <= "000000000000000" & keyboard(4);
						when "0111" =>
							dataOut <= "000000000000000" & keyboard(3);
						when "1000" =>
							dataOut <= "000000000000000" & keyboard(2);
						when "1001" =>
							dataOut <= "000000000000000" & keyboard(1);
						when "1010" =>
							dataOut <= "000000000000000" & keyboard(0);
						when others => 
							dataOut <= "0000000000000000";
					end case;
                                        rd <= '1';
				else 
                                        rd <= '0';
                                        dataOut <= dIn;
                                  
			        end if;
                          else              
                               rd <= '1';
                               dataOut <= dIn;             
			       
		end if;

	end process;

end Behavioral;
